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Synchronisation to the DCF77 “atomic” clock in Frankfurt

DCF77 receiver module available from the Shockwaves shop on ebay



DCF77 decoder board


Circuit Description

This circuit decodes the data-stream from a DCF77 clock module.  The clock module receives the DCF77 signal transmitted from Mainflingen near Frankfurt Germany and outputs a data-stream containing demodulated timing information. 

The circuit will provide a precise 1 min clock pulse that can be used to synchronise an electronic clock. 

Built using CMOS IC’s and a few other components the circuit is simple enough to be built onto Strip board or a PCB if required.  

Error checking is built into the circuit so that any noise pulses received during a 1 minute frame or any missing pulses will cause the frame to be rejected. 

Pulse and circuit status is indicated by a series of LEDs .

Circuit Detail

Full circuit details can be found in the master clock documentation in word or pdf format

Download full Master Clock doc file



Download the pdf file






Main Master Clock showing DCF77 status LEDs installed near bottom left of display

Master Clock


Close-up of DCF77 decoder status LEDs



The DCF77 Signal

DCF77  0 to 59 secs







Start of minute, always 0.


Civil warning bits, provided by the Bundesamt
für Bevölkerungsschutz und Katastrophenwarnung
(Federal Office of Civil Protection and Disaster Relief).
Also contain weather broadcasts.
















Call bit, set during abnormal transmitter operation.
Previously indicated use of the backup antenna.



Summer time announcement.
Set during hour before change.



Set to 1 when CEST is in effect.



Set to 1 when CET is in effect.



Leap second announcement.
Set during hour before leap second.



Start of encoded time, always 1.


















Even parity over seconds 21–28.
















Even parity over seconds 29–35.



Day of month.













Day of week
Monday=1, Sunday=7







Month number











Year within century

















Even parity over seconds 36–58.


0 bit transmitted immediately before leap seconds.


No bit transmitted during last second of each minute.



The time is represented in binary-coded decimal. It represents civil time, including summer time adjustments. The time transmitted is the time of the following minute; e.g. during Dec 31 23:59, the transmitted time encodes Jan 1 00:00.

The first 20 seconds are special flags. The minutes are encoded in seconds 21–28, hours during seconds 29–34, and the date during seconds 36–58.

Two flags warn of changes to occur at the end of the current hour: a change of time zones, and a leap second insertion. These flags are set during the hour up to the event. This includes the last minute before the event, during which the other time code bits (including the time zone indicator bits) encode the time of the first minute after the event.




Although the time code only includes two digits of the year, it is possible to deduce two bits of the century using the day of week. There is still a 400-year ambiguity, as the Gregorian calendar repeats weeks every 400 years.

The time zone bits can be considered a binary-coded representation of the GMT offset. Z1 set indicates UTC+2, while Z2 indicates UTC+1. XE "Diagram DCF77 pulse make up"


This circuit uses the 100mS and 200mS pulses along with the break on the 59th second to decode the 1 min time intervals.



Circuit Detail XE "DCF77 Circuit Detail"

Initial power up.

On initial power up the DCF77 synchronises itself to the incoming 77.5KHz signal from Frankfurt and outputs 0 volts while this is in progress.


The low output from the DCF77 module make the “Frame Sync” LED will light followed by the “Pulse Error LED” showing that no pulses are being received.



0 volts at the DCF77 input in inverted twice through IC2f & IC2e and output as 0 volts to D5. Capacitor C1 will therefore discharge through VR1 to earth. As the voltage discharges inverters IC4c & IC2a will trigger.

IC4a triggering causes the “Frame Sync” LED to illuminate.

IC2a triggering causes C8 to charge through R8. Eventually IC2d will trigger low when the charge across C8 is large enough.

The low from IC2d cause the “Pulse error” LED to illuminate due to the low on inverter IC4d.


Normal operation

The pulses from the DCF77 are 100ms & 200ms spaced at 1 second intervals except the 59th second where no pulse is transmitted. This indicates the end of frame.

The circuit counts the incoming pulses and when 58 pulses have successfully been received waits to make sure no further pulses are received in the 59th second then outputs a pulse (1 min) when the first pulse of the frame is received. The missing pulse on the 59th second is indicated by the “Frame sync” LED illuminating. The LED will illuminate until the 1st pulse in the new frame is received.

This pulse also resets the count so it can start again from the 2nd frame pulse.


DCF77 monitor LEDs showing normal operation with a missing pulse at 59sec and sync at 60sec


Detail  "Diagram DCF77 error fast pulse"

The pulses from the DCF77 are received through R11 and if their duration is long enough will cause C6 to charge and to trigger IC2f.


The “1 sec pulse” LED will illuminate to show pulses are being received. Inverter IC2e outputs the pulses to IC1 that counts the pulses and transfers them to it’s binary coded outputs 1-7.


The pulses from IC2e also charge C1 via VR1, R1 and D5. "Diagram DCF77 error too long pulse"

DCF77 status LEDs showing error on fast pulse. Note there will be no 1 min sync pulse generated.




After a few pulses C1 will have enough charge and the “Frame sync” LED will be extinguished due to IC4c going low.

IC2a will go low as C1 is charged. This will cause C8 to discharge making IC2d go high. AND IC3a is held off due to this low from IC2a on pin 2.

IC2d going high causes the “Pulse error” LED to extinguish via inverter IC4d.

Inverter IC4a goes low and removes the high on the reset pin of IC1 so it can start to count the incoming pulses.

IC1 counts the incoming pulses and when it counts to 58 the outputs 2, 4, 5 and 6 go high. This corresponds to binary 2, 8, 16 and 32. These outputs are connected to the cathodes of diodes D1 to D4. While any output from IC1 is low i.e. not 58 R7 pin 2 is held low. At 58 all outputs connected to the diodes D1 to D4 go high and R7 pin 2 can now go high


 "Diagram DCF77 error too many pulses" .

Therefore AND IC3b pin 6 goes high but output stays low as pin 5 is still low from IC3a.

Pulse 59 is blank so IC1 stays at 58 during the 59th pulse and AND IC3B pin 6 remains high.

During the 59th pulse which is blank IC2e goes low and C1 starts to discharge through VR1. During the blank pulse with C1 discharged IC2 a goes high.

IC2a will start charging C8 via R8 but under normal pulse condition will not charge enough to make IC2d output go low.


IC2a going high makes IC3a pin 2 high. IC3a remains low as pin 1 is still low.

The 1st pulse is then received from IC2e now the AND gate IC3a goes high as pin 1 is now high and pin 2 was high from the missing pulse at 59 seconds.




IC2a remains high until approx 0.47 seconds through the first pulse as C1 charges through R1.

IC3a going high makes AND gate IC3b pin 5 high. IC3b now goes high as pin 6 was held high by the 58 count on IC1. Thus a 1 sec pulse is generated on the 1 pulse of the frame.

IC1 is reset via IC2b delayed by R3 & C3 ready for the 2nd pulse (this is why IC1 counts to 58 not 59).  XE "Diagram DCF77 reset"



  Reset. While IC3a sits low and IC2c sits high IC1 will not reset due to C5 and R12 holding low.  When IC3a goes hi for 100ms IC2 goes low. At the end of the 100ms pulse IC2c goes high and resets IC1 delayed by 10µ Sec R3 & C3.

Pulse and Circuit Monitor LEDs XE "Diagram DCF77 LED monitors"



The following pulses are monitored by using inverters IC4b,c,d,e&f.


1 sec pulse illuminates when pulses are being received from the DCF77 module.


Frame sync illuminates when a break of around 1.7 seconds is detected. Normally this is the 59th pulse.


Pulse error illuminates on a pulse break of more than 1.7 seconds or a pulse greater than 200m seconds.


1 min pulse will illuminate to show a 1 min pulse has been generated.



Error Checking XE "DCF77 Error Checking"

Short pulse less than 100mS.



The shortest pulse of 100mS should be enough to charge C8 through R11 to trigger IC2f. Any shorter pulse will not trigger IC2f.

IC2e inverts signal from IC2f .




Long pulse greater than 200ms XE "DCF77 Long pulse greater than 200ms" .



  Normally R10 & C7 will discharge every pulse. If a longer pulse than 200ms is received then C7 will charge through R10 and cause IC2d to go low. This is inverted high by IC4a and the counter is reset and the frame is rejected as IC1 will not count to 58 in time for the break on the 59th pulse. R9 pulls IC2d low when C7 is not high.



  Long pulse break XE "Long pulse break"


Any pulse break greater than 1.8 seconds is an error. As IC2a goes high on receipt of the 1.8 sec break on the 59th second C8 begins to charge through R8. If IC2 does not go low due to due to a new pulse being received C8 will charge enough to make IC2d go low. IC4a now goes high and resets IC1 via diode D10.


DCF77 status LEDs showing error on slow or missing pulse. Note there will be no 1 min sync pulse generated.



  Too many pulses


Pulses from IC2e step the binary counter. When the counter reaches 58 IC2b goes low.

If another pulse is received (58 pulses should be followed by a missing pulse) the counter is reset. IC2b goes high resetting IC1.



Video showing DCF77 decoder LEDs & Synchronization of the Master Clock