Atomic Time Synchronisation Circuit Slave Clocks Calendar Clock Slave Voltmeter Clock LCD Master Clock Master Clock Mk2 Guestbook
Download full Master Clock doc file
Download the pdf file
Master clock Synchronized to the DCF77 "Atomic" Clock in Frankfurt
1” High Brightness 7 segments display of Hours, Minutes and
24 Hour transistor switched pulse output with diode protection
1 Hour transistor switched pulse output with diode protection
30 Second transistor switched pulse output with diode protection
Seconds reset and pause for precise clock setting
30 Second pulse can be synchronised with clock display at 00 &
Hourly Chime with switch for silent night time running
The Master clock can run any number of slaves by adding extra relays/transistors
Master Clock video in HD
Complete Master Clock System Master & Slave Dials
|Animated video showing Master Clock and Slaves at midnight and shows how the calendar steps round at the end of the month||Animated video showing Master Clock and Slaves at midnight and shows the calendar stepping ahead 1 day|
|Master Clock Construction Details|
|Download Master Clock Diagrams|
7 segment displays are driven and controlled by CMOS ICs. The time is kept
by a 32.768KHz Quartz Crystal.
are mounted on Tripad Board and fitted in an Oak case.
Time Display Diagram 1
circuit uses 4026B Decade counter, decoder and display driver ICs to drive the 7
segment displays and decode the time.
1 second pulse from (diagram 2) is connected to the input pin 1 of
IC11. This IC counts from 1-0 and displays the seconds units via the LED
display. When the count reaches 0 on the 10th pulse the IC resets and
outputs a pulse to IC9 input pin 1. This advances the seconds tens display by 1.
Every 10 seconds IC9 is stepped by 1 until the count reaches 60 seconds or 6
pulses to IC9. IC9 & 11 are reset by IC2d and IC12a. This reset also steps
the Minute Units by 1 via the Set Secs switch not operated, IC7a and IC7b to IC8
minute unit segment is stepped every minute and as per the seconds unit it will
be reset at 0 and pulse the minute tens segment. Again when the minutes tens
segment steps to 6 (60 minutes have elapsed)
the minutes are reset IC6 & 8 via IC2 b&c. A pulse is also sent
to the hours display via IC3 b&c to IC5 pin1.
hours units are therefore pulsed every hour. When the hours units IC5 reaches 0
it pulses the hours tens IC1. This
continues until the hours units reaches 4 and the hours tens reaches 2 (24:00).
The logic ICs IC2a & IC4a then reset IC1 & IC5.
can be reset by operating the reset button SW3. This applies +ve to the reset
pins of IC 9 & 11 to reset the seconds display.
seconds can also be stopped by operating SW4 this resets the divide by 2
counter. The seconds pulse is stopped as long as SW4 is held.
30 second sync pulse
pulse is produced every 60 seconds from the reset pulse from
IC2d and IC12a. This is used to synchronise the display with a 30 second
1 Hour Pulse
is produced by the reset pulse from IC2b & IC2c. This is fed out externally
via IC6c & IC6d and the output transistor TR2.
24 Hour Pulse
is produced by the reset pulse from IC2a & IC4a. This pulse is used to
synchronise the hourly chime at midnight.
is fed out externally via IC12c & IC12d and the output transistor TR3.
1 Second Pulse Diagram 2
1 second pulse is derived from a 4060 14 stage binary ripple counter IC with a
built in oscillator. The oscillator is driven by a 32.768Khz Quartz crystal.
4060 divides the 32.768Khz by 2 to the power of 14. This gives a 2Hz output from
this IC at pin 3. The 2Hz pulses are then fed into IC5 a Binary counter. The
output from pin 12 (divide by 2) is used as a 1 second pulse.
30 Second Pulse Diagram 2
1 second pulse is fed into IC1 a 4017 decade counter/divider IC. Every 10
seconds IC1 pulses IC2. When IC2 receives 3 pulses (every 30 seconds) the IC is
reset and a pulse is sent out on pin 7.
30 Second Pulse Synchronisation Diagram
30 second pulse can be synchronised with the display by operating SW1 until the
seconds read 00. SW1 should then be released. When operated SW1 connects the
reset pins of IC1 & 2 to the 60 sec pulse. This pulse is produced when the
seconds display reaches 60 so IC 1 & 2 are therefore reset as the display
reaches 60 and are then in perfect sync.
pulses that drive external devices go through logic ICs configured as
monostables. These monstable control the shape and timing of the pulses. The
monostables then drive medium power transistors with diode protection so they
can drive relays etc.
30 second pulse output can drive 1 30second clock. You can connect as many as
you want by using external relays or power transistors.
30 Seconds Slave Clock Control Diagram
slave clocks are controlled by SW5. In its normal position SW5 connects the 30
second pulse to the drive transistors so the clocks pulse as normal. SW5a lights
the Gn LED “30sec clocks ON”. Note this LED lights rather than the RED led
due to the extra voltage drop across the RED led and diode. The “30 sec” LED
will also pulse to show the cct is working.
SW5 set to “Retard” the 30 second pulse is disconnected from the drive
transistors and the slave clocks stop. Note slave clocks cannot be stepped
backwards. To set clocks for winter time the clocks are stopped for 1 hour. SW5a
disconnects the Green “30sec clocks ON” LED and allows the Red “Retard”
LED to light. Note on operating SW5 the clocks will step forward 1 pulse or
30seconds. This is useful for fine setting the slave clocks.
SW5 set to “Advance” the slave clocks are advanced every second. SW5
connects the 1 second pulse to the drive transistors. The “30 sec” LED will
light every second to show the slave clocks are being advanced.
Second & 30 Second Pulse Generator with drive circuits
Master clock showing display board and external connections on main board below.
The quartz crystal trimmer capacitor is just visible above the white label bottom left.
Three silver toggle switches for 30sec synchronisation, advance & retard of 30sec slaves and chime on & off can
be seen above the white label to the bottom right.
The labels for the display are on a 2nd sheet of glass spaced 1mm from the front glass. Dry transfers were used for the lettering.
Hourly Chime Circuit
chime circuit uses 2 CMOS 4516 Binary Up Down Counters to count then pulse
out the hourly chime. The chime pulses drive a miniature relay with a
copper wire soldered to the armature as the hammer. The bell is from an
old telephone but any bell or gong can be used.
Hourly Chime Diagram 3
1 hour pulse is fed into the chime setting circuit at IC7c and out through
IC7b. From IC7b the pulse is fed to IC5a one of a pair of D Type Flip
Flops CMOS 4013. These flip flops are configured as Monostables. The not Q
output is fed to IC5b the other Monostable pair.
Q output is fed to IC1 4516 configured to count up.
Q output is fed to IC2 4516 configured to count down.
Note there is a delay between the Q outputs on IC5a and IC5b see
Q output from IC5a steps IC1 up by 1 every hour pulse. This count is sent
to IC2 via its BCD inputs from IC1. IC2 is now set at the count from IC1.
the delayed Q output from IC5b is received at IC2 it will start to count
down to 0. The delay allows IC1 to count up and set IC2 before IC2 counts
down to 0. Chime count down is monitored by LEDs 6,7,8 & 9 and is
displayed in BCD format.
chime rate is set to 1 second and is fed from the 1 second pulse to IC4b
& c to the drive transistor. The 1 second pulse is also fed back to
the input of IC2 via inverter IC3d to count this IC down. When IC2 has
counted down the 1 second feed to the drive transistor is turned off using
logic via the inverter IC3b.
the Master clock displays in 24 hour format the chime will sound in 12
hour format. IC3a, IC3b & IC4a are logic gates that detect the 13th
hourly pulse and then set IC1 back to 1.
setting up the clock the chime has to be synchronised with the display.
IC7a, b, c & d are set up as a noiseless switch and by pressing and
releasing SW1 the chime is advanced by 1. The chime will sound out each
time SW1 is depressed but there is no need to wait for this just keep
pressing SW1 until the BCD LED display shows the same hour as the clock.
The chime is now set and will chime out as the main clock display hits the
ensure the chime remains synchronised with the display the 24 hour pulse
is used to synchronise the chime at midnight. IC6a & b again
configured as monstables are used for this purpose.
Chime Setting Diagram 3 cont.
midnight the 24 hour pulse is fed to the monostable IC6a. The Q output is
fed to the D input of IC6b on the 1 second clock pulse. The Q output from
IC6b is then used to reset IC1 again on the 1 or 2 sec second clock pulse. IC1 is
now reset with enough delay to send BCD 12 to IC2 and also IC2 is allowed
to pulse out 12 to the chime transistor.
Control Diagram 3
chime can be turned on and off by SW2. When SW2 is on it simply connects
the chime relay to the supply rail. When SW2 is off the chime relay is
disconnected and the chime off LED is connected instead to the supply
Chime board mounted on the top of the master clock.
Note tri-pad board has been sprayed green before mounting the components and wiring.
Chime via a min relay and telephone bell. This has a nice sound as is very compact but is not very loud.
Chime via a 4" longcase clock bell and 30sec clock movement. This option gives out a very loud chime but takes up a lot of space. I have fitted it into the case of my longcase clock and disabled the longcase clock chime.
This contains the
display ICs and logic and is made using Tripad board.
Oscillator Board front and back
The oscillator board
is mounted away from the main board in a position that is easy to reach so
the oscillator can be adjusted to 32.768KHz.
The oscillator is
effected by temperature but should be able to keep time well within a
second a week at room temperature.
crystal accuracy against
temperatue graph for standard and temperature compensated types
If the clock is used
in building with wide temperature variations then a temperature
compensated crystal should be used. In the graph above you can see the
temperature compensated crystal is flat from -40˚C to 80˚C.
If DCF77 synchronization is used then (see below) then problem with quartz
accuracy can be ignored.
If DCF77 synchronization is used then (see below) then problem with quartz accuracy can be ignored.
Master Clock Display